Messages in this thread | | | Date | Mon, 9 Jan 2023 01:23:54 +0200 | Subject | Re: [PATCH v2 1/8] drm/msm/dpu: Wire up DSC mask for active CTL configuration | From | Dmitry Baryshkov <> |
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On 22/12/2022 01:19, Marijn Suijten wrote: > Active CTLs have to configure what DSC block(s) have to be enabled, and > what DSC block(s) have to be flushed; this value was initialized to zero > resulting in the necessary register writes to never happen (or would > write zero otherwise). This seems to have gotten lost in the DSC v4->v5 > series while refactoring how the combination with merge_3d was handled. > > Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder") > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 + > 2 files changed, 2 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-- With best wishes Dmitry
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