Messages in this thread | | | From | Jernej Škrabec <> | Subject | Re: [PATCH] clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock | Date | Sun, 08 Jan 2023 21:54:38 +0100 |
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Dne četrtek, 29. december 2022 ob 05:22:30 CET je Samuel Holland napisal(a): > The DRAM controller clock is only allowed to change frequency while the > DRAM chips are in self-refresh. To support this, changes to the CLK_DRAM > mux and divider have no effect until acknowledged by the memory dynamic > frequency scaling (MDFS) hardware inside the DRAM controller. (There is > a SDRCLK_UPD bit in DRAM_CFG_REG which should serve a similar purpose, > but this bit actually does nothing.) > > However, the MDFS hardware in H3 appears to be broken. Triggering a > frequency change using the procedure from similar SoCs (A64/H5) hangs > the hardware. Additionally, the vendor BSP specifically avoids using the > MDFS hardware on H3, instead performing all DRAM PHY parameter updates > and resets in software. > > Thus, it is effectively impossible to change the CLK_DRAM mux/divider, > so those features should not be modeled. Add CLK_SET_RATE_PARENT so > frequency changes apply to PLL_DDR instead. > > Signed-off-by: Samuel Holland <samuel@sholland.org>
Applied, thanks!
Best regards, Jernej
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