Messages in this thread | | | Date | Thu, 5 Jan 2023 19:55:42 +0200 | From | Vladimir Oltean <> | Subject | Re: [PATCH net-next v5 4/4] phy: aquantia: Determine rate adaptation support from registers |
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On Thu, Jan 05, 2023 at 07:52:06PM +0200, Vladimir Oltean wrote: > On Thu, Jan 05, 2023 at 12:43:47PM -0500, Sean Anderson wrote: > > Again, this is to comply with the existing API assumptions. The current > > code is buggy. Of course, another way around this is to modify the API. > > I have chosen this route because I don't have a situation like you > > described. But if support for that is important to you, I encourage you > > to refactor things. > > I don't think I'm aware of a practical situation like that either. > I remember seeing some S32G boards with Aquantia PHYs which use 2500BASE-X > for 2.5G and SGMII for <=1G, but that's about it in terms of protocol switching. > As for Layerscape boards, SERDES protocol switching is a very new concept there, > so they're all going to be provisioned for PAUSE all the way down > (or USXGMII, where that is available). > > I just pointed this out because it jumped out to me. I don't have > something against this patch getting accepted as it is.
A real-life (albeit niche) scenario where someone might have an Aquantia firmware provisioned like this would be a 10G capable port that also wants to support half duplex at 10/100 speeds. Although I'm not quite sure who cares about half duplex all that much these days.
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