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SubjectRe: [PATCH] riscv, kprobes: Stricter c.jr/c.jalr decoding
Thx for catching it.

On Tue, Jan 3, 2023 at 12:07 AM Björn Töpel <bjorn@kernel.org> wrote:
>
> From: Björn Töpel <bjorn@rivosinc.com>
>
> In the compressed instruction extension, c.jr, c.jalr, c.mv, and c.add
> is encoded the following way (each instruction is 16b):
>
> ---+-+-----------+-----------+--
> 100 0 rs1[4:0]!=0 00000 10 : c.jr
> 100 1 rs1[4:0]!=0 00000 10 : c.jalr
> 100 0 rd[4:0]!=0 rs2[4:0]!=0 10 : c.mv
> 100 1 rd[4:0]!=0 rs2[4:0]!=0 10 : c.add
Yes, I forgot the c.mv & c.add effect.

Reviewed-by: Guo Ren <guoren@kernel.org>

>
> The following logic is used to decode c.jr and c.jalr:
>
> insn & 0xf007 == 0x8002 => instruction is an c.jr
> insn & 0xf007 == 0x9002 => instruction is an c.jalr
>
> When 0xf007 is used to mask the instruction, c.mv can be incorrectly
> decoded as c.jr, and c.add as c.jalr.
>
> Correct the decoding by changing the mask from 0xf007 to 0xf07f.
>
> Fixes: c22b0bcb1dd0 ("riscv: Add kprobes supported")
> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
> ---
> arch/riscv/kernel/probes/simulate-insn.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h
> index cb6ff7dccb92..de8474146a9b 100644
> --- a/arch/riscv/kernel/probes/simulate-insn.h
> +++ b/arch/riscv/kernel/probes/simulate-insn.h
> @@ -31,9 +31,9 @@ __RISCV_INSN_FUNCS(fence, 0x7f, 0x0f);
> } while (0)
>
> __RISCV_INSN_FUNCS(c_j, 0xe003, 0xa001);
> -__RISCV_INSN_FUNCS(c_jr, 0xf007, 0x8002);
> +__RISCV_INSN_FUNCS(c_jr, 0xf07f, 0x8002);
> __RISCV_INSN_FUNCS(c_jal, 0xe003, 0x2001);
> -__RISCV_INSN_FUNCS(c_jalr, 0xf007, 0x9002);
> +__RISCV_INSN_FUNCS(c_jalr, 0xf07f, 0x9002);
> __RISCV_INSN_FUNCS(c_beqz, 0xe003, 0xc001);
> __RISCV_INSN_FUNCS(c_bnez, 0xe003, 0xe001);
> __RISCV_INSN_FUNCS(c_ebreak, 0xffff, 0x9002);
>
> base-commit: 1b929c02afd37871d5afb9d498426f83432e71c2
> --
> 2.37.2
>


--
Best Regards
Guo Ren

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