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SubjectRe: [PATCH 1/1] iommu/vt-d: Set No Execute Enable bit in PASID table entry
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On 2023/1/28 15:19, Tian, Kevin wrote:
>> From: Lu Baolu<baolu.lu@linux.intel.com>
>> Sent: Thursday, January 26, 2023 5:55 PM
>>
>> Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
>> entry. It is required when XD bit of the first level page table
>> entry is about to be set.
> "is about to set" sounds like the NXE bit is set conditionally when
> certain event happens. But the actual definition of NXE bit is to
> allow the use of XD bit of the first level page table.
>
> With the comment fixed:
>
> Reviewed-by: Kevin Tian<kevin.tian@intel.com>

Updated. Thank you, Kevin.

Best regards,
baolu

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