Messages in this thread | | | Date | Fri, 27 Jan 2023 10:36:06 +0000 | From | Lee Jones <> | Subject | Re: [PATCH v6 05/11] mfd: intel-m10-bmc: Support multiple CSR register layouts |
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On Mon, 16 Jan 2023, Ilpo Järvinen wrote:
> There are different addresses for the MAX10 CSR registers. Introducing > a new data structure m10bmc_csr_map for the register definition of > MAX10 CSR. > > Provide the csr_map for SPI. > > Co-developed-by: Tianfei zhang <tianfei.zhang@intel.com> > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> > Reviewed-by: Russ Weight <russell.h.weight@intel.com> > Reviewed-by: Xu Yilun <yilun.xu@intel.com> > Acked-for-MFD-by: Lee Jones <lee@kernel.org> > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > --- > drivers/fpga/intel-m10-bmc-sec-update.c | 73 +++++++++++++++++-------- > drivers/mfd/intel-m10-bmc-core.c | 10 ++-- > drivers/mfd/intel-m10-bmc-spi.c | 23 ++++++++ > include/linux/mfd/intel-m10-bmc.h | 38 +++++++++++-- > 4 files changed, 111 insertions(+), 33 deletions(-)
Applied, thanks
-- Lee Jones [李琼斯]
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