Messages in this thread Patch in this message | | | From | Yazen Ghannam <> | Subject | [PATCH v2 15/22] EDAC/amd64: Split read_mc_regs() into dct/umc functions | Date | Fri, 27 Jan 2023 17:04:12 +0000 |
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From: Muralidhara M K <muralidhara.mk@amd.com>
...and call them from their respective hw_info_get() paths.
ECC symbol size is not needed on UMC systems, so determine_ecc_sym_sz() is left out of the UMC path.
Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com> Co-developed-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com> [Rebased/reworked patch and reworded commit message] Co-developed-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> --- Link: https://lore.kernel.org/r/20220509145534.44912-11-yazen.ghannam@amd.com
v1->v2: * Call functions directly instead of using pointers.
drivers/edac/amd64_edac.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0d0e563c99db..757d35fad2a6 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3089,7 +3089,7 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt) /* * Retrieve the hardware registers of the memory controller. */ -static void __read_mc_regs_df(struct amd64_pvt *pvt) +static void umc_read_mc_regs(struct amd64_pvt *pvt) { u8 nid = pvt->mc_node_id; struct amd64_umc *umc; @@ -3113,7 +3113,7 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) * Retrieve the hardware registers of the memory controller (this includes the * 'Address Map' and 'Misc' device regs) */ -static void read_mc_regs(struct amd64_pvt *pvt) +static void dct_read_mc_regs(struct amd64_pvt *pvt) { unsigned int range; u64 msr_val; @@ -3134,12 +3134,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) edac_dbg(0, " TOP_MEM2 disabled\n"); } - if (pvt->umc) { - __read_mc_regs_df(pvt); - - goto skip; - } - amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); read_dram_ctl_register(pvt); @@ -3180,9 +3174,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); } -skip: - - determine_ecc_sym_sz(pvt); } @@ -3658,7 +3649,7 @@ static int dct_hw_info_get(struct amd64_pvt *pvt) dct_prep_chip_selects(pvt); dct_read_base_mask(pvt); - read_mc_regs(pvt); + dct_read_mc_regs(pvt); dct_determine_memory_type(pvt); return 0; @@ -3672,7 +3663,7 @@ static int umc_hw_info_get(struct amd64_pvt *pvt) umc_prep_chip_selects(pvt); umc_read_base_mask(pvt); - read_mc_regs(pvt); + umc_read_mc_regs(pvt); umc_determine_memory_type(pvt); return 0; -- 2.25.1
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