Messages in this thread Patch in this message | | | From | Bjorn Andersson <> | Subject | [PATCH v2 3/3] arm64: dts: qcom: sa8295p-adp: Add max20411 on i2c12 | Date | Tue, 24 Jan 2023 10:44:40 -0800 |
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From: Bjorn Andersson <bjorn.andersson@linaro.org>
The SA8295P ADP has a Maxim max20411 step-down converter on i2c12.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> ---
Changes since v1: - i2c node had changed name
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index bb4270e8f551..642000d95812 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -266,6 +266,27 @@ &dispcc1 { status = "okay"; }; +&i2c12 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_state>; + + status = "okay"; + + vdd_gfx: regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + regulator-name = "vdd_gfx"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <968750>; + + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&vdd_gfx_enable_state>; + }; +}; + &mdss0 { status = "okay"; }; @@ -476,6 +497,10 @@ &pcie4_phy { status = "okay"; }; +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -636,7 +661,23 @@ &xo_board_clk { /* PINCTRL */ +&pmm8540a_gpios { + vdd_gfx_enable_state: vdd-gfx-enable-state { + pins = "gpio2"; + function = "normal"; + output-enable; + }; +}; + &tlmm { + i2c12_state: i2c12-state { + pins = "gpio0", "gpio1"; + function = "qup12"; + + drive-strength = <2>; + bias-pull-up; + }; + pcie2a_default: pcie2a-default-state { clkreq-n-pins { pins = "gpio142"; -- 2.25.1
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