Messages in this thread | | | Date | Tue, 24 Jan 2023 02:24:07 +0200 | Subject | Re: [PATCH Resend v11 11/15] drm/msm/disp/dpu: get timing engine status from intf status register | From | Dmitry Baryshkov <> |
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On 19/01/2023 16:26, Vinod Polimera wrote: > Recommended way of reading the interface timing gen status is via > status register. Timing gen status register will give a reliable status > of the interface especially during ON/OFF transitions. This support was > added from DPU version 5.0.0.
5.0.0 is sm8150. I have expected to see INTF_SC7180_MASK to be changed, while this patch for some reason changes only INTF_SC7280_MASK. Could you please clarify this?
> > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 +++++++----- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++++++- > 3 files changed, 16 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 4375e72..0244a7b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -80,7 +80,8 @@ > > #define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) > > -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) > +#define INTF_SC7280_MASK \ > + (INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_STATUS_SUPPORTED)) > > #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > BIT(MDP_SSPP_TOP0_INTR2) | \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 978e3bd..79c18fe 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -213,17 +213,19 @@ enum { > > /** > * INTF sub-blocks > - * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which > - * pixel data arrives to this INTF > - * @DPU_INTF_TE INTF block has TE configuration support > - * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate > - than video timing > + * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which > + * pixel data arrives to this INTF > + * @DPU_INTF_TE INTF block has TE configuration support > + * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate > + * than video timing > + * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register > * @DPU_INTF_MAX > */ > enum { > DPU_INTF_INPUT_CTRL = 0x1, > DPU_INTF_TE, > DPU_DATA_HCTL_EN, > + DPU_INTF_STATUS_SUPPORTED, > DPU_INTF_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 7ce66bf..84ee2ef 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -62,6 +62,7 @@ > #define INTF_LINE_COUNT 0x0B0 > > #define INTF_MUX 0x25C > +#define INTF_STATUS 0x26C > > #define INTF_CFG_ACTIVE_H_EN BIT(29) > #define INTF_CFG_ACTIVE_V_EN BIT(30) > @@ -297,8 +298,13 @@ static void dpu_hw_intf_get_status( > struct intf_status *s) > { > struct dpu_hw_blk_reg_map *c = &intf->hw; > + unsigned long cap = intf->cap->features; > + > + if (cap & BIT(DPU_INTF_STATUS_SUPPORTED)) > + s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0); > + else > + s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); > > - s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN); > s->is_prog_fetch_en = !!(DPU_REG_READ(c, INTF_CONFIG) & BIT(31)); > if (s->is_en) { > s->frame_count = DPU_REG_READ(c, INTF_FRAME_COUNT);
-- With best wishes Dmitry
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