Messages in this thread | | | Date | Tue, 17 Jan 2023 15:02:29 +0530 | Subject | Re: [PATCH v7 7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node | From | Siddharth Vadapalli <> |
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Hello Achal,
On 17/01/23 14:53, Achal Verma wrote: > Tue, Nov 29, 2022 at 11:53:46AM -0600, Andrew Davis wrote: >> On 11/22/22 4:16 AM, Matt Ranostay wrote: >>> From: Aswath Govindraju <a-govindraju@ti.com> >>> >>> Add PCIe1 RC device tree node for the single PCIe instance present on >>> the j721s2. >>> >>> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> >>> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> >>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >>> Signed-off-by: Matt Ranostay <mranostay@ti.com> >>> --- >>> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 41 ++++++++++++++++++++++ >>> 1 file changed, 41 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi >>> index 2858ba589d54..27631ef32bf5 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi >>> @@ -841,6 +841,47 @@ serdes0: serdes@5060000 { >>> }; >>> }; >>> + pcie1_rc: pcie@2910000 { >> >> NIT: Not sure we need to call this "_rc", and "1", 0 index these names for >> consistency, "pcie0". > > Sure, I will name this node as "pcie0_rc" in next patch and "_rc" is because it can be used in endpoint mode too for which "pcie0_ep" node can be added in future.
The naming is based on the PCIe instance documented in the Technical Reference Manual (TRM). For example, consider J7200 SoC which has "pcie1_rc" even though it has no "pcie0_rc". This convention is based on the numbering used in the TRM.
Regards, Siddharth.
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