Messages in this thread |  | | Subject | Re: [PATCH] coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR | From | hejunhao <> | Date | Sat, 14 Jan 2023 16:49:29 +0800 |
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On 2023/1/12 11:48, Anshuman Khandual wrote: > > On 1/10/23 18:21, Junhao He wrote: >> The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the > s/register is/registers are/ Ok, will fix it. Thanks. >> TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases. > s/register/registers/ Ok, will fix it. Thanks.
>> Signed-off-by: Junhao He <hejunhao3@huawei.com> > Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> > >> --- >> .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++++------ >> 1 file changed, 12 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index 80fefaba58ee..c7a65d1524fc 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -424,8 +424,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) >> etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); >> - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); >> for (i = 0; i < drvdata->nr_cntr; i++) { >> etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); >> @@ -1631,8 +1633,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); >> >> - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); >> + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); >> + } >> state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); >> >> for (i = 0; i < drvdata->nr_cntr; i++) { >> @@ -1760,8 +1764,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) >> for (i = 0; i < drvdata->nrseqstate - 1; i++) >> etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); >> >> - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + if (drvdata->nrseqstate) { >> + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); >> + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); >> + } >> etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); >> >> for (i = 0; i < drvdata->nr_cntr; i++) { > . >
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