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SubjectRe: [PATCH v5 15/17] qcom: llcc/edac: Fix the base address used for accessing LLCC banks
On Wed, Dec 28, 2022 at 02:10:26PM +0530, Manivannan Sadhasivam wrote:
> The Qualcomm LLCC/EDAC drivers were using a fixed register stride for
> accessing the (Control and Status Registers) CSRs of each LLCC bank.
> This stride only works for some SoCs like SDM845 for which driver
> support was initially added.
> But the later SoCs use different register stride that vary between the
> banks with holes in-between. So it is not possible to use a single register
> stride for accessing the CSRs of each bank. By doing so could result in a
> crash.

If this patch fixes a crash, then it should be

Cc: <>

If there are prerequisites to it, they should be CC:stable too.

So looking at the urgent stuff: patches 1, 3, I'm thinking I can take them
through the EDAC tree and send them to Linus now, after you've addressed the
review comments.

This one can go through some other tree, I presume, but since it fixes a crash
it should go in now too...

> For fixing this issue, let's obtain the base address of each LLCC bank from
> devicetree and get rid of the fixed stride. This also means, we no longer

Please use passive voice in your commit message: no "we" or "I", etc,
and describe your changes in imperative mood.

Personal pronouns are ambiguous in text, especially with so many
parties/companies/etc developing the kernel so let's avoid them please.

> need to rely on reg-names property and get the base addresses using index.
> First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC
> supports more than one bank, then those needs to be defined in devicetree


> for index from 1..N-1.
> Reported-by: Parikshit Pareek <>
> Tested-by: Luca Weiss <>
> Tested-by: Steev Klimaszewski <> # Thinkpad X13s
> Tested-by: Andrew Halaney <> # sa8540p-ride
> Signed-off-by: Manivannan Sadhasivam <>

With the above addressed, for the EDAC bits:

Reviewed-by: Borislav Petkov (AMD) <>



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