Messages in this thread | | | From | <> | Subject | Re: [PATCH net-next v6 6/6] dsa: lan9303: Migrate to PHYLINK | Date | Thu, 12 Jan 2023 05:22:57 +0000 |
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Hi Jerry, On Mon, 2023-01-09 at 15:18 -0600, Jerry Ray wrote: > > diff --git a/drivers/net/dsa/lan9303-core.c > b/drivers/net/dsa/lan9303-core.c > index 7be4c491e5d9..e514fff81af6 100644 > --- a/drivers/net/dsa/lan9303-core.c > +++ b/drivers/net/dsa/lan9303-core.c > @@ -1058,37 +1058,6 @@ static int lan9303_phy_write(struct dsa_switch > *ds, int phy, int regnum, > return chip->ops->phy_write(chip, phy, regnum, val); > } > > +static void lan9303_phylink_get_caps(struct dsa_switch *ds, int > port, > + struct phylink_config *config) > +{ > + struct lan9303 *chip = ds->priv; > + > + dev_dbg(chip->dev, "%s(%d) entered.", __func__, port); > + > + config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE | > + MAC_SYM_PAUSE; > + > + if (port == 0) { > + __set_bit(PHY_INTERFACE_MODE_RMII, > + config->supported_interfaces); > + __set_bit(PHY_INTERFACE_MODE_MII, > + config->supported_interfaces); > + } else { > + __set_bit(PHY_INTERFACE_MODE_INTERNAL, > + config->supported_interfaces); > + /* Compatibility for phylib's default interface type > when the > + * phy-mode property is absent > + */ > + __set_bit(PHY_INTERFACE_MODE_GMII, > + config->supported_interfaces); > + } > + > + /* This driver does not make use of the speed, duplex, pause or > the > + * advertisement in its mac_config, so it is safe to mark this > driver > + * as non-legacy. > + */ > + config->legacy_pre_march2020 = false; > +} > + > +static void lan9303_phylink_mac_link_up(struct dsa_switch *ds, int > port, > + unsigned int mode, > + phy_interface_t interface, > + struct phy_device *phydev, int > speed, > + int duplex, bool tx_pause, > + bool rx_pause) > +{ > + u32 ctl; > + > + /* On this device, we are only interested in doing something > here if > + * this is the xMII port. All other ports are 10/100 phys using > MDIO > + * to control there link settings. > + */ > + if (port != 0) > + return; > + > + ctl = lan9303_phy_read(ds, port, MII_BMCR); > + > + ctl &= ~BMCR_ANENABLE; > + > + if (speed == SPEED_100) > + ctl |= BMCR_SPEED100; > + else if (speed == SPEED_10) > + ctl &= ~BMCR_SPEED100; > + else > + dev_err(ds->dev, "unsupported speed: %d\n", speed);
I think, We will not reach in the error part, since in the phylink_get_caps we specified only 10 and 100 Mbps speed. Phylink layer will validate and if the value is beyond the speed supported, it will return back.
> + > + if (duplex == DUPLEX_FULL) > + ctl |= BMCR_FULLDPLX; > + else > + ctl &= ~BMCR_FULLDPLX; > + > + lan9303_phy_write(ds, port, MII_BMCR, ctl); > +} > + >
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