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    Subject[PATCH v5 00/14] PolarFire SoC reset controller & clock cleanups
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    @Stephen, even if you do not take the rest of the series for v6.1, the
    first patch is a bugfix for boot failures that can be trigged with v6.0
    so even if you have reservations about the aux device stuff, I would
    appreciate if you would take the first patch.

    Unfortunately, the rest of the series does have a conflict with/depends
    on the fix - so if you do take it on -fixes could you do it as a commit
    on top of -rc1 so the rest of the series will apply?

    Thanks,
    Conor.

    Original Cover:
    Hey all,

    Kinda two things happening in this series, but I sent it together to
    ensure the second part would apply correctly.

    The first is the reset controller that I promised after discovering the
    issue triggered by CONFIG_PM & the phy not coming up correctly. I have
    now removed all the messing with resets from clock enable/disable
    functions & now use the aux bus to set up a reset controller driver.
    Since I needed something to test it, I hooked up the reset for the
    Cadence MACB on PolarFire SoC. This has been split into a second series
    for v2 (and is now in v6.0-rcN):
    https://lore.kernel.org/all/20220704114511.1892332-1-conor.dooley@microchip.com/

    The second part adds rate control for the MSS PLL clock, followed by
    some simplifications to the driver & conversions of some custom structs
    to the corresponding structs in the framework.

    I'll take the dts patch myself when the rest of this is okay-ed.
    Thanks,
    Conor.

    Changes since v4:
    - use the alternative macro Claudiu suggested for patch 1
    - drop a ~useless intermediate variable in mpfs_deassert()

    Changes since v3:
    - return results directly in probe() & reset_controller_register()

    Changes since v2:
    - reorder reset Makefile/Kconfig entries
    - fix a pre-existing bug exposed by clang with this series applied
    - add Padmarao who co-authored the original driver to the authors

    Conor Dooley (14):
    clk: microchip: mpfs: fix clk_cfg array bounds violation
    clk: microchip: mpfs: make the rtc's ahb clock critical
    dt-bindings: clk: microchip: mpfs: add reset controller support
    clk: microchip: mpfs: add reset controller
    reset: add polarfire soc reset support
    MAINTAINERS: add polarfire soc reset controller
    riscv: dts: microchip: add mpfs specific macb reset support
    clk: microchip: mpfs: add MSS pll's set & round rate
    clk: microchip: mpfs: move id & offset out of clock structs
    clk: microchip: mpfs: simplify control reg access
    clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()
    clk: microchip: mpfs: convert cfg_clk to clk_divider
    clk: microchip: mpfs: convert periph_clk to clk_gate
    clk: microchip: mpfs: update module authorship & licencing

    .../bindings/clock/microchip,mpfs.yaml | 17 +-
    MAINTAINERS | 1 +
    arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +-
    drivers/clk/microchip/Kconfig | 1 +
    drivers/clk/microchip/clk-mpfs.c | 384 +++++++++---------
    drivers/reset/Kconfig | 7 +
    drivers/reset/Makefile | 2 +-
    drivers/reset/reset-mpfs.c | 157 +++++++
    include/soc/microchip/mpfs.h | 8 +
    9 files changed, 388 insertions(+), 196 deletions(-)
    create mode 100644 drivers/reset/reset-mpfs.c


    base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
    --
    2.36.1

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