Messages in this thread | | | From | Jim Mattson <> | Date | Wed, 7 Sep 2022 09:29:29 -0700 | Subject | Re: [PATCH v2 2/3] KVM: x86/pmu: Limit the maximum number of supported Intel GP counters |
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On Wed, Sep 7, 2022 at 3:49 AM Like Xu <like.xu.linux@gmail.com> wrote: > > From: Like Xu <likexu@tencent.com> > > The Intel Architectural IA32_PMCx MSRs addresses range allows for > a maximum of 8 GP counters. A local macro (named KVM_INTEL_PMC_MAX_GENERIC) > is introduced to take back control of this virtual capability to avoid > errors introduced by the out-of-bound counter emulations. > > Suggested-by: Jim Mattson <jmattson@google.com> > Signed-off-by: Like Xu <likexu@tencent.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
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