Messages in this thread | | | From | Linus Walleij <> | Date | Tue, 6 Sep 2022 15:09:32 +0200 | Subject | Re: [PATCH v6 1/1] gpio: mpfs: add polarfire soc gpio support |
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On Mon, Sep 5, 2022 at 12:45 PM <Lewis.Hanly@microchip.com> wrote: > On Wed, 2022-08-31 at 15:19 +0200, Linus Walleij wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you > > know the content is safe > > > > On Tue, Aug 30, 2022 at 6:51 AM <Lewis.Hanly@microchip.com> wrote: > > > > > We had looked at the bpgpio_init, our controller is not fully > > > memory > > > mapped to support the bgpio_init() and get all routines for free. > > > While we have in/out and intr (interrupt state) 32-bit registers, > > > we > > > would not get as much free as other generic memory mapped > > > controllers. > > > > You're not really saying what the problem is? > > > > Is it that some registers are not one-bit-indexed from 0 per GPIO? > Yes some of the registers are not one-bit-indexed per GPIO and for this > reason we had not implemented bgpio_init().
OK that's a valid reason not to use that. Thanks! The regmap may help though, have a look!
Yours, Linus Walleij
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