Messages in this thread | | | Date | Tue, 6 Sep 2022 05:54:40 +0100 | From | Oliver Upton <> | Subject | Re: [PATCH v2 7/7] KVM: selftests: Add test for RAZ/WI AArch32 ID registers |
| |
Hi Drew,
On Mon, Sep 05, 2022 at 09:31:40AM +0200, Andrew Jones wrote:
[...]
> > +static uint64_t reg_ids[] = { > > + KVM_ARM64_SYS_REG(SYS_ID_PFR0_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_PFR1_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_MMFR0_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_MMFR1_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_MMFR2_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_MMFR3_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_ISAR0_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_ISAR1_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_ISAR2_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_ISAR3_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_ISAR4_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_ISAR5_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_MMFR4_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_ISAR6_EL1), > > + KVM_ARM64_SYS_REG(SYS_MVFR0_EL1), > > + KVM_ARM64_SYS_REG(SYS_MVFR1_EL1), > > + KVM_ARM64_SYS_REG(SYS_MVFR2_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_PFR2_EL1), > > + KVM_ARM64_SYS_REG(SYS_ID_MMFR5_EL1), > > Hi Oliver, > > I see all the hidden and unallocated registers have been filtered out of > the test lists. They should also behave as RAZ, right? Maybe we should > keep them in the lists here for consistency and to test them as well.
Sure, can do. The reason I only tested these registers is because they have RAZ/WI behavior with this series, whereas the rest are RAZ + invariant. Should be easy enough to cover the whole range, though.
-- Thanks, Oliver
| |