Messages in this thread Patch in this message | | | From | Zong Li <> | Subject | [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts | Date | Mon, 5 Sep 2022 08:31:22 +0000 |
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Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level.
Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> --- drivers/soc/sifive/sifive_ccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 1b16a196547f..0e0eb85c94d8 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -38,6 +38,7 @@ static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; +static int level; enum { DIR_CORR = 0, @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = { static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf) { /* We want to use private group for composable cache only */ - if (this_leaf->level == 2) + if (this_leaf->level == level) return &priv_attr_group; else return NULL; @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void) if (!ccache_base) return -ENOMEM; + if (of_property_read_u32(np, "cache-level", &level)) + return -ENODEV; + intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("CCACHE: no interrupts property\n"); -- 2.17.1
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