Messages in this thread | | | From | MandyJH Liu (劉人僖) <> | Subject | Re: [PATCH v3 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents | Date | Fri, 30 Sep 2022 05:59:41 +0000 |
| |
On Tue, 2022-09-27 at 12:11 +0200, AngeloGioacchino Del Regno wrote: > These PLLs are conflicting with GPU rates that can be generated by > the GPU-dedicated MFGPLL and would require a special clock handler > to be used, for very little and ignorable power consumption benefits. > Also, we're in any case unable to set the rate of these PLLs to > something else that is sensible for this task, so simply drop them: > this will make the GPU to be clocked exclusively from MFGPLL for > "fast" rates, while still achieving the right "safe" rate during > PLL frequency locking. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> > --- > drivers/clk/mediatek/clk-mt8195-topckgen.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c > b/drivers/clk/mediatek/clk-mt8195-topckgen.c > index 4dde23bece66..8cbab5ca2e58 100644 > --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c > +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c > @@ -298,11 +298,14 @@ static const char * const ipu_if_parents[] = { > "mmpll_d4" > }; > > +/* > + * MFG can be also parented to "univpll_d6" and "univpll_d7": > + * these have been removed from the parents list to let us > + * achieve GPU DVFS without any special clock handlers. > + */ > static const char * const mfg_parents[] = { > "clk26m", > - "mainpll_d5_d2", > - "univpll_d6", > - "univpll_d7" > + "mainpll_d5_d2" > }; > > static const char * const camtg_parents[] = { There might be a problem here. Since the univpll_d6 and univpll_d7 are available parents in hardware design and they can be selected other than kernel stage, like bootloader, the clk tree listed in clk_summary cannot show the real parent-child relationship in such case.
| |