Messages in this thread | | | Date | Fri, 30 Sep 2022 13:57:46 +0300 | Subject | Re: [PATCH v2 11/11] phy: qcom-qmp-pcie: drop bogus register update | From | Dmitry Baryshkov <> |
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On 29/09/2022 12:29, Johan Hovold wrote: > Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the > PHY is powered on before configuring the registers and only the MSM8996 > PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS > initialisation table, may possibly require a second update afterwards. > > To make things worse, the POWER_DOWN_CONTROL register lies at a > different offset on more recent SoCs so that the second update, which > still used a hard-coded offset, would write to an unrelated register > (e.g. a revision-id register on SC8280XP). > > As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop > the bogus register update. > > Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support > Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #RB3
-- With best wishes Dmitry
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