Messages in this thread | | | Date | Thu, 29 Sep 2022 18:36:53 -0700 | Subject | Re: [PATCH v5 1/3] drm/msm/dp: cleared DP_DOWNSPREAD_CTRL register before start link training | From | Abhinav Kumar <> |
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On 9/12/2022 12:25 PM, Dmitry Baryshkov wrote: > On 12/09/2022 22:21, Kuogee Hsieh wrote: >> >> On 9/12/2022 11:39 AM, Dmitry Baryshkov wrote: >>> On 12/09/2022 19:23, Kuogee Hsieh wrote: >>>> DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an >>>> upstream device disconnect. This patch will enforce this rule by always >>>> cleared DOWNSPREAD_CTRL register to 0 before start link training. At >>>> rare >>>> case that DP MSA timing parameters may be mis-interpreted by the sink >>>> which causes audio sampling rate be calculated wrongly and cause audio >>>> did not work at sink if DOWNSPREAD_CTRL register is not cleared to 0. >>>> >>>> Changes in v2: >>>> 1) fix spelling at commit text >>>> 2) merge ssc variable into encoding[0] >>>> >>>> Changes in v3: >>>> -- correct spelling of DOWNSPREAD_CTRL >>>> -- replace err with len of ssize_t >>>> >>>> Changes in v4: >>>> -- split into 2 patches >>>> >>>> Fixes: 154b5a7da0fd ("drm/msm/dp: add displayPort driver support")
Fixes tag is wrong here. It should be:
Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support")
>>>> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> >>>> --- >>>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 13 +++++-------- >>>> 1 file changed, 5 insertions(+), 8 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c >>>> b/drivers/gpu/drm/msm/dp/dp_ctrl.c >>>> index ab6aa13..2c74c59 100644 >>>> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c >>>> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c >>>> @@ -1245,8 +1245,7 @@ static int dp_ctrl_link_train(struct >>>> dp_ctrl_private *ctrl, >>>> { >>>> int ret = 0; >>>> const u8 *dpcd = ctrl->panel->dpcd; >>>> - u8 encoding = DP_SET_ANSI_8B10B; >>>> - u8 ssc; >>>> + u8 encoding[] = { 0, DP_SET_ANSI_8B10B }; >>>> u8 assr; >>>> struct dp_link_info link_info = {0}; >>>> @@ -1258,13 +1257,11 @@ static int dp_ctrl_link_train(struct >>>> dp_ctrl_private *ctrl, >>>> dp_aux_link_configure(ctrl->aux, &link_info); >>>> - if (drm_dp_max_downspread(dpcd)) { >>>> - ssc = DP_SPREAD_AMP_0_5; >>>> - drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1); >>>> - } >>>> + if (drm_dp_max_downspread(dpcd)) >>>> + encoding[0] |= DP_SPREAD_AMP_0_5; >>> >>> It would be simpler to call drm_dp_dpcd_write(ssc, >>> DP_DOWNSPREAD_CTRL, 1) unconditionally here. You won't have to change >>> the encoding/DP_MAIN_LINK_CHANNEL_CODING_SET/etc. >> >> The difference is one write with 2 bytes against two writes with one >> byte each. >> >> I think it is more efficient to combine two bytes into one write since >> these two bytes are consecutive address. > > I probably wouldn't do so, nevertheless: > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > >> >>> >>>> - drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, >>>> - &encoding, 1); >>>> + /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */ >>>> + drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); >>>> if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { >>>> assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; >>> >
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