Messages in this thread | | | Date | Tue, 27 Sep 2022 12:39:45 +0200 | Subject | Re: [PATCH 5/6] clk: mediatek: mt8192: deduplicate parent clock lists | From | AngeloGioacchino Del Regno <> |
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Il 26/09/22 12:25, Chen-Yu Tsai ha scritto: > Some groups of clocks of the same type share the same list of parents. > These lists were declared separately for each clock in older drivers, > bloating the code. > > Merge some obvious duplicate parent clock lists in the MT8192 clock > driver together to reduce the code size. These include: > > - apll_i2s*_m_parents into one as apll_i2s_m_parents > - img1_parents & img2_parents into one as img_parents > - msdc30_*_parents into one as msdc30_parents > - camtg*_parents into cam_tg_parents > - seninf*_parents into seninf_parents > > Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Makes a lot of sense, agreed.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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