Messages in this thread Patch in this message | | | From | Prabhakar <> | Subject | [RFC PATCH 2/2] clk: renesas: r9a07g044: Mark CRU_SYSCLK and CRU_VCLK as no PM | Date | Tue, 27 Sep 2022 21:30:44 +0100 |
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular sequence for the CRU block hence use DEF_NO_PM() to set the no_pm flag.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- drivers/clk/renesas/r9a07g044-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 6935441f7504..31b1437c57e4 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -252,9 +252,9 @@ static const struct { 0x558, 1), DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 0x558, 2), - DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2, + DEF_NO_PM("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2, 0x564, 0), - DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2, + DEF_NO_PM("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2, 0x564, 1), DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT, 0x564, 2), -- 2.25.1
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