lkml.org 
[lkml]   [2022]   [Sep]   [26]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH v3 10/11] remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout
Date
The MT8195 SCP core 1 watchdog timeout needs to be handled in the
SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout
IRQ is wired on the same IRQ entry for core 0 watchdog timeout.
MT8195 SCP has a watchdog status register to identify the watchdog
timeout source when IRQ triggered.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
drivers/remoteproc/mtk_common.h | 4 +++
drivers/remoteproc/mtk_scp.c | 44 ++++++++++++++++++++++++++++++++-
2 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index dcde25f8bbf9..6cd04ca9e681 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -55,6 +55,10 @@
#define MT8192_CORE0_WDT_IRQ 0x10030
#define MT8192_CORE0_WDT_CFG 0x10034

+#define MT8195_SYS_STATUS 0x4004
+#define MT8195_CORE0_WDT BIT(16)
+#define MT8195_CORE1_WDT BIT(17)
+
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)

#define MT8195_CPU1_SRAM_PD 0x1084
diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index 0f1b587f8502..159f3c69cd69 100644
--- a/drivers/remoteproc/mtk_scp.c
+++ b/drivers/remoteproc/mtk_scp.c
@@ -222,6 +222,48 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
}
}

+static void mt8195_scp_irq_handler(struct mtk_scp *scp)
+{
+ u32 scp_to_host;
+
+ scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET);
+
+ if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
+ scp_ipi_handler(scp);
+ } else {
+ if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) {
+ struct device_node *c1_np;
+ struct platform_device *c1_pdev;
+ struct mtk_scp *c1_scp;
+
+ writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ);
+
+ c1_np = of_get_compatible_child(scp->dev->of_node,
+ "mediatek,mt8195-scp-core");
+ if (!c1_np) {
+ dev_err(scp->dev, "cannot find core 1 node\n");
+ goto clear_irq;
+ }
+
+ c1_pdev = of_find_device_by_node(c1_np);
+ of_node_put(c1_np);
+ if (!c1_pdev) {
+ dev_err(scp->dev, "cannot find core 1 pdev\n");
+ goto clear_irq;
+ }
+
+ c1_scp = platform_get_drvdata(c1_pdev);
+ scp_wdt_handler(c1_scp, scp_to_host);
+ } else {
+ writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ);
+ scp_wdt_handler(scp, scp_to_host);
+ }
+ }
+
+clear_irq:
+ writel(scp_to_host, scp->reg_base + MT8192_SCP2APMCU_IPC_CLR);
+}
+
static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp)
{
u32 scp_to_host;
@@ -1155,7 +1197,7 @@ static const struct mtk_scp_of_data mt8192_of_data = {
static const struct mtk_scp_of_data mt8195_of_data = {
.scp_clk_get = mt8195_scp_clk_get,
.scp_before_load = mt8195_scp_before_load,
- .scp_irq_handler = mt8192_scp_irq_handler,
+ .scp_irq_handler = mt8195_scp_irq_handler,
.scp_reset_assert = mt8192_scp_reset_assert,
.scp_reset_deassert = mt8192_scp_reset_deassert,
.scp_stop = mt8195_scp_stop,
--
2.18.0
\
 
 \ /
  Last update: 2022-09-27 05:00    [W:0.231 / U:0.084 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site