Messages in this thread | | | Date | Mon, 26 Sep 2022 13:18:00 -0500 | From | Bjorn Helgaas <> | Subject | Re: [PATCH V2 8/9] phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration |
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On Mon, Sep 26, 2022 at 05:20:37PM +0530, Vidya Sagar wrote: > Set ENABLE_L2_EXIT_RATE_CHANGE to request UPHY PLL rate change to Gen1 > during initialization. This helps in the below surprise down cases, > - Surprise down happens at Gen3/Gen4 link speed > - Surprise down happens and external REFCLK is cut off which causes > UPHY PLL rate to deviate to an invalid rate > > ENABLE_L2_EXIT_RATE_CHANGE needs to be set to bring the UPHY PLL rate > back to Gen1 during controller initialization for the link up. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Reported-by: kernel test robot <lkp@intel.com>
I doubt the kernel test robot reported the issue being fixed by this patch. More likely it reported a syntax or similar issue in v1, and I think the "reported-by" tag is meaningless in cases like that.
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