Messages in this thread Patch in this message | | | From | Vidya Sagar <> | Subject | [PATCH V2 3/9] PCI: tegra194: Fix polling delay for L2 state | Date | Mon, 26 Sep 2022 17:20:32 +0530 |
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Current L2 state polling with 1us interval is too aggressive. Based on the experiments with different endpoints, LTSSM state transisition to L2 is happening between 6us ~ 40us. Hence, update the polling delay for L2 state from 1us to 100us for a better utilization of CPU cycles.
Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V2: * None
drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7721f920dd74..7d6e54a12eff 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -206,7 +206,8 @@ #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK GENMASK(11, 8) #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT 8 -#define PME_ACK_TIMEOUT 10000 +#define PME_ACK_DELAY 100 /* 100 us */ +#define PME_ACK_TIMEOUT 10000 /* 10 ms */ #define LTSSM_TIMEOUT 50000 /* 50ms */ @@ -1556,7 +1557,7 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, val & APPL_DEBUG_PM_LINKST_IN_L2_LAT, - 1, PME_ACK_TIMEOUT); + PME_ACK_DELAY, PME_ACK_TIMEOUT); } static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) -- 2.17.1
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