Messages in this thread | | | Date | Thu, 22 Sep 2022 11:38:09 +0200 | From | Miquel Raynal <> | Subject | Re: [mtd:nand/next 11/31] drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit declaration of function 'ioread64_rep' is invalid in C99 |
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Hi Arnd,
> > ioread64_rep is then only defined if CONFIG_64BIT. As it is based > > on readsq/writesq() and those must be defined (as you said), I don't get > > why the *64_rep() helpers are not defined in all cases. Maybe because no > > 32-bit system _should_ need them? But then compile testing gets more > > difficult. > > Both readsq/writesq and ioread64_rep/iowrite64_rep must be defined > for 64-bit architectures and cannot be defined for 32-bit ones.
Yeah, ok.
> >> - For a FIFO, you cannot use readq() but have to use __raw_readq() > >> to get the correct endianness. You cannot use this for an > >> MMIO register with side-effects though, as this needs the byteswap > >> and the barrier in readsl(). > > > > I'm not sure about the true definition of "FIFO" as you say. I guess > > you just mean reading from a BE device? > > > > In this case I guess we need the barrier+byteswap helpers. > > The difference is that a register has a fixed length, and gets > accessed with a device specific endianness, which may have to > be swapped if the device and the CPU disagree. > > A FIFO register is what you use for transferring a stream of > bytes, such as reading a file system block from disk. The > first byte in the register corresponds to the first byte in > memory later, so there must not be any byteswap while copying > to/from memory. If the data itself is structured (i.e. an > on-disk inode or a network packet), then the byteswap will > happen if necessary while interpreting the data.
Ok, I fully get what you mean, I was just not used to the word FIFO for this definition as I use it as a more generic term, but it completely makes sense. Thanks for taking the time to explain.
Thanks, Miquèl
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