Messages in this thread Patch in this message | | | From | Dinh Nguyen <> | Subject | [PATCHv2 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" | Date | Thu, 22 Sep 2022 17:03:06 -0500 |
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Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: added --- .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..aece6a337262 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -38,6 +38,18 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + description: + Contains the phandle to System Manager block that contains + the SDMMC clock-phase control register. The first value is the pointer + to the sysmgr and the 2nd value is the register offset for the SDMMC + clock phase register. + required: - compatible - reg -- 2.25.1
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