Messages in this thread | | | Date | Wed, 21 Sep 2022 19:56:25 +0800 | Subject | Re: [PATCH V5 08/11] riscv: Support HAVE_IRQ_EXIT_ON_IRQ_STACK | From | Chen Zhongjin <> |
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Hi,
Sorry to bother again, I just finished the test with your patches on mine patch set.
On 2022/9/21 17:53, Guo Ren wrote: > On Wed, Sep 21, 2022 at 4:34 PM Chen Zhongjin <chenzhongjin@huawei.com> wrote: >> Hi, >> >> On 2022/9/18 23:52, guoren@kernel.org wrote: >>> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S >>> index 5f49517cd3a2..426529b84db0 100644 >>> --- a/arch/riscv/kernel/entry.S >>> +++ b/arch/riscv/kernel/entry.S >>> @@ -332,6 +332,33 @@ ENTRY(ret_from_kernel_thread) >>> tail syscall_exit_to_user_mode >>> ENDPROC(ret_from_kernel_thread) >>> >>> +#ifdef CONFIG_IRQ_STACKS >>> +ENTRY(call_on_stack) >>> + /* Create a frame record to save our ra and fp */ >>> + addi sp, sp, -RISCV_SZPTR >>> + REG_S ra, (sp) >>> + addi sp, sp, -RISCV_SZPTR >>> + REG_S fp, (sp) >>> + >>> + /* Save sp in fp */ >>> + move fp, sp >>> +
Considering that s0 points to previous sp normally, I think here we should have 'addi fp, sp, 2*RISCV_SZPTR'.
An example below:
addi sp, sp, -16 sd ra, 8(sp) sd s0, 0(sp) addi s0, sp, 16 <- s0 is set to previous sp ...
ld ra,8(sp) ld s0,0(sp) addi sp,sp,16
So maybe it's better to save the stack frame as below:
addi sp, sp, -2*RISCV_SZPTR REG_S ra, RISCV_SZPTR(sp) REG_S s0, (sp)
/* Save sp in fp */ addi s0, sp, 2*RISCV_SZPTR
...
/* * Restore sp from prev fp, and fp, ra from the frame */ addi sp, s0, -2*RISCV_SZPTR REG_L ra, RISCV_SZPTR(sp) REG_L s0, (sp) addi sp, sp, 2*RISCV_SZPTR
Anyway, lets set fp as sp + 2 * RISCV_SZPTR, so that unwinder can connect two stacks same as normal function.
I tested this with my patch and the unwinder works properly.
Thanks for your time!
Best,
Chen
>>> + /* Move to the new stack and call the function there */ >>> + li a3, IRQ_STACK_SIZE >>> + add sp, a1, a3 >>> + jalr a2 >>> + >>> + /* >>> + * Restore sp from prev fp, and fp, ra from the frame >>> + */ >>> + move sp, fp >>> + REG_L fp, (sp) >>> + addi sp, sp, RISCV_SZPTR >>> + REG_L ra, (sp) >>> + addi sp, sp, RISCV_SZPTR >>> + ret >>> +ENDPROC(call_on_stack) >>> +#endif >> Seems my compiler (riscv64-linux-gnu-gcc 8.4.0, cross compiling from >> x86) cannot recognize the register `fp`. > The whole entry.S uses s0 instead of fp, so I approve of your advice. Thx. > >> After I changed it to `s0` this can pass compiling. >> >> >> Seems there is nowhere else using `fp`, can this just using `s0` instead? >> >> Best, >> >> Chen >> >>
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