Messages in this thread | | | Date | Thu, 22 Sep 2022 11:20:55 +0900 | From | Jiho Chu <> | Subject | Re: [PATCH v2 13/13] dt-bindings: arm: Add Samsung Trinity bindings |
| |
On Wed, 21 Sep 2022 20:42:35 +0200 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote:
> On 17/09/2022 09:23, Jiho Chu wrote: > > The Trinity Neural Processing Unit (NPU) is a hardware IP for providing > > hardware acceleration for neural network processing workloads. It has > > own virtual ISA decoder unit, and controlled by memory mapped control > > registers. The IP is composed of Common Processor (CP), Digital Signal > > Processor (DSP) and Deep Learning Accelerator (DLA). ComBox is register > > set to control IRQ or check overall status of the IP. > > > > Signed-off-by: Jiho Chu <jiho.chu@samsung.com> > > Signed-off-by: Yelin Jeong <yelini.jeong@samsung.com> > > Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> > > --- > > .../bindings/arm/samsung,trinity.yaml | 115 ++++++++++++++++++ > > 1 file changed, 115 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/arm/samsung,trinity.yaml > > > > diff --git a/Documentation/devicetree/bindings/arm/samsung,trinity.yaml b/Documentation/devicetree/bindings/arm/samsung,trinity.yaml > > new file mode 100644 > > index 000000000000..cd79ec040162 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/arm/samsung,trinity.yaml > > @@ -0,0 +1,115 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: https://protect2.fireeye.com/v1/url?k=d6ad487f-b7d0a003-d6acc330-74fe485cc33c-c18489118cc5693c&q=1&e=e1fcd741-e7bc-4610-b982-e9d1481f4eb1&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Farm%2Fsamsung%2Ctrinity.yaml%23 > > +$schema: https://protect2.fireeye.com/v1/url?k=eceeef8d-8d9307f1-ecef64c2-74fe485cc33c-c540319d368eacda&q=1&e=e1fcd741-e7bc-4610-b982-e9d1481f4eb1&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23 > > + > > +title: Samsung Trinity NPU Family > > + > > +maintainers: > > + - Jiho Chu <jiho.chu@samsung.com> > > + > > +description: | > > + The Trinity Neural Processing Unit (NPU) is a hardware IP for providing > > + hardware acceleration for neural network processing workloads. It has > > + own virtual ISA decoder unit, and controlled by memory mapped control > > + registers. The IP is composed of Common Processor (CP), Digital Signal > > + Processor (DSP) and Deep Learning Accelerator (DLA). ComBox is register > > + set to control IRQ or check overall status of the IP. > > + > > +properties: > > + compatible: > > + const: samsung,trinity > > + > > + samsung,trinity-type: > > + description: type of trinity family > > + enum: ['triv2'] > > No, we have compatible for this. >
This property will be removed.
> > + > > + samsung,tops: > > + description: Performance metric (Tera Operation Per Seconds) > > + enum: [2, 8] > > What piece of hardware this describes? >
This is related to HW internal structure, but it can be matched from compotible property. I'll add more value for compitable, and this will be removed.
> > + > > + samsung,idu_cp: > > No underscores in names. > > Missing ref/type. Missing description. I am not sure that this belongs > to DT. > > > > + items: > > + - description: Address of zero data of CP > > + - description: Address of IDU data of CP > > + - description: Maximum size of CP's IDU binary > > > + > > + samsung,idu_dsp: > > The same. >
underscore will be fixed like (samsung,idu,xxxx)
> > + items: > > + - description: Address of zero data of DSP > > + - description: Address of IDU data of DSP > > + - description: Maximum size of DSP's IDU binary > > + > > + samsung,dspm: > > + description: The size of Data Scratch-Pad Memory > > + > > + memory-region: > > + description: > > + phandle to the reserved memory node to be associated > > + with the trinity device. The reserved memory node > > + can be a CMA memory node. > > + Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml > > + > > + dma-coherent: true > > + > > + reg: > > + items: > > + - description: Memory mapped register of CP > > + - description: Memory mapped register of DSP > > + - description: Memory mapped register of ComBox > > + > > + reg-names: > > + items: > > + - const: cp-mmreg > > + - const: dsp-mmreg > > + - const: cbox-mmreg > > Drop "reg" suffixes. >
OK.
> > + > > + interrupts: > > + description: workload complete interrupt > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - samsung,trinity-type > > + - samsung,tops > > + - samsung,idu_cp > > + - samsung,idu_dsp > > + - samsung,dspm > > + - memory-region > > + - dma-coherent > > + - reg > > + - reg-names > > + - interrupts > > + > > +examples: > > + - | > > + reserved-memory { > > + #address-cells = <2>; > > + #size-cells = <1>; > > + trinity_dram_0: memory@80000000 { > > + compatible = "shared-dma-pool"; > > + no-map; > > + reg = <0x0 0x80000000 0x10000000>; > > + }; > > + }; > > Drop this part - it is fairly obvious. >
OK.
> > + > > + triv2@0x30C00000 { > > + compatible = "samsung,trinity"; > > + samsung,trinity-type = "triv2"; > > + samsung,tops = <8>; > > + samsung,idu_cp = /bits/ 64 <0x30400000 0x30400010 0x10000>; > > + samsung,idu_dsp = /bits/ 64 <0x30500000 0x30500010 0x10000>; > > + samsung,dspm = <0x40000>; > > + > > + memory-region = <&trinity_dram_0> > > + > > + dma-coherent; > > + > > + reg = <0x0 0x30C10000 0x0 0x10000>, /* CP MMREG base */ > > + <0x0 0x30D40000 0x0 0x10000>, /* DSP MMREG base */ > > + <0x0 0x30DF0000 0x0 0x01000>; /* ComBox MMREG base */ > > > reg and reg-names go after compatible. >
OK.
> > + reg-names = "cp-mmreg", "dsp-mmreg", "cbox-mmreg"; > > + > > + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > Best regards, > Krzysztof > >
Hi, Krzysztof Thanks for your review.
Best regards, Jiho Chu
| |