Messages in this thread | | | Date | Wed, 21 Sep 2022 18:07:11 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v2 2/3] x86/cpufeatures: Introduce X86_FEATURE_NO_LMSLE |
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On Tue, Sep 20, 2022 at 01:59:21PM -0700, Jim Mattson wrote: > When AMD introduced "Long Mode Segment Limit Enable" (a.k.a. "VMware > mode"), the feature was not enumerated by a CPUID bit. Now that VMware > has abandoned binary translation, AMD has deprecated EFER.LMSLE. > > The absence of the feature *is* now enumerated by a CPUID bit (a la > Intel's X86_FEATURE_ZERO_FCS_DCS and X86_FEATURE_FDP_EXCPTN_ONLY). > > This defeature bit is already present in feature word 13, but it was > previously anonymous. Name it X86_FEATURE_NO_LMSLE, so that KVM can > reference it when constructing a supported guest CPUID table. > > Since this bit indicates the absence of a feature, don't enumerate it > in /proc/cpuinfo. > > Signed-off-by: Jim Mattson <jmattson@google.com> > --- > arch/x86/include/asm/cpufeatures.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index ef4775c6db01..0f5a3285d8d8 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -319,6 +319,7 @@ > #define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */ > #define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */ > #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */ > +#define X86_FEATURE_NO_LMSLE (13*32+20) /* "" EFER_LMSLE is unsupported */ > #define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */ > #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ > #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ > --
Acked-by: Borislav Petkov <bp@suse.de>
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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