Messages in this thread | | | From | Andy Shevchenko <> | Date | Fri, 2 Sep 2022 10:20:08 +0300 | Subject | Re: [PATCH v2 1/2] gpio: Add gpio latch driver |
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On Fri, Sep 2, 2022 at 10:16 AM Sascha Hauer <s.hauer@pengutronix.de> wrote: > On Fri, Sep 02, 2022 at 09:42:21AM +0300, Andy Shevchenko wrote: > > On Wed, Aug 31, 2022 at 9:02 AM Sascha Hauer <s.hauer@pengutronix.de> wrote: > > > > > > This driver implements a GPIO multiplexer based on latches connected to > > > other GPIOs. A set of data GPIOs is connected to the data input of > > > multiple latches. The clock input of each latch is driven by another > > > set of GPIOs. With two 8-bit latches 10 GPIOs can be multiplexed into > > > 16 GPIOs. GPOs might be a better term as in fact the multiplexed pins > > > are output only. > > > > So, this is for only one type of latches, now I'm wondering why > > gpio-74xx-mmio can't cover this case (with probably small > > modifications to the code)? > > gpio-74xx-mmio is about latches connected to a parallel bus. You can > access the GPIOs by doing readl/writel operations. The latches are > driven by the bus logic and likely an additional address decoder. > > What I have here instead is a latch fully driven by GPIOs.
But this reminds me of some kind of gpio-aggregator with a specific layer on top. To me it really feels that we are (semi-)reinventing a wheel between the lines...
> Yes, with enough force you could implement it in the gpio-74xx-mmio > driver, but that wouldn't be mmio at all and likely completely different > code pathes.
Got it, thanks for elaboration.
-- With Best Regards, Andy Shevchenko
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