lkml.org 
[lkml]   [2022]   [Sep]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Date
SubjectRe: [PATCH v2 1/4] riscv: Add X register names to gpr-nums
On Wed, Aug 31, 2022 at 10:55 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> When encoding instructions it's sometimes necessary to set a
> register field to a precise number. This is easiest to do using
> the x<num> naming.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>

I have queued this patch for Linux-6.1

Thanks,
Anup

> ---
> arch/riscv/include/asm/gpr-num.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/riscv/include/asm/gpr-num.h b/arch/riscv/include/asm/gpr-num.h
> index dfee2829fc7c..efeb5edf8a3a 100644
> --- a/arch/riscv/include/asm/gpr-num.h
> +++ b/arch/riscv/include/asm/gpr-num.h
> @@ -3,6 +3,11 @@
> #define __ASM_GPR_NUM_H
>
> #ifdef __ASSEMBLY__
> +
> + .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
> + .equ .L__gpr_num_x\num, \num
> + .endr
> +
> .equ .L__gpr_num_zero, 0
> .equ .L__gpr_num_ra, 1
> .equ .L__gpr_num_sp, 2
> @@ -39,6 +44,9 @@
> #else /* __ASSEMBLY__ */
>
> #define __DEFINE_ASM_GPR_NUMS \
> +" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n" \
> +" .equ .L__gpr_num_x\\num, \\num\n" \
> +" .endr\n" \
> " .equ .L__gpr_num_zero, 0\n" \
> " .equ .L__gpr_num_ra, 1\n" \
> " .equ .L__gpr_num_sp, 2\n" \
> --
> 2.37.2
>

\
 
 \ /
  Last update: 2022-09-02 08:53    [W:0.106 / U:0.776 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site