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    Subject[PATCH v2 02/23] KVM: SVM: Flush the "current" TLB when activating AVIC
    From
    Flush the TLB when activating AVIC as the CPU can insert into the TLB
    while AVIC is "locally" disabled. KVM doesn't treat "APIC hardware
    disabled" as VM-wide AVIC inhibition, and so when a vCPU has its APIC
    hardware disabled, AVIC is not guaranteed to be inhibited. As a result,
    KVM may create a valid NPT mapping for the APIC base, which the CPU can
    cache as a non-AVIC translation.

    Note, Intel handles this in vmx_set_virtual_apic_mode().

    Signed-off-by: Sean Christopherson <seanjc@google.com>
    ---
    arch/x86/kvm/svm/avic.c | 6 ++++++
    1 file changed, 6 insertions(+)

    diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
    index 6919dee69f18..4fbef2af1efc 100644
    --- a/arch/x86/kvm/svm/avic.c
    +++ b/arch/x86/kvm/svm/avic.c
    @@ -86,6 +86,12 @@ static void avic_activate_vmcb(struct vcpu_svm *svm)
    /* Disabling MSR intercept for x2APIC registers */
    svm_set_x2apic_msr_interception(svm, false);
    } else {
    + /*
    + * Flush the TLB, the guest may have inserted a non-APIC
    + * mappings into the TLB while AVIC was disabled.
    + */
    + kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu);
    +
    /* For xAVIC and hybrid-xAVIC modes */
    vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID;
    /* Enabling MSR intercept for x2APIC registers */
    --
    2.37.2.789.g6183377224-goog
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