Messages in this thread Patch in this message | | | From | <> | Subject | Re: [PATCH 1/4] riscv: cleanup svpbmt cpufeature probing | Date | Fri, 2 Sep 2022 15:26:21 +0000 |
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On 02/09/2022 16:12, Heiko Stübner wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Am Freitag, 2. September 2022, 11:49:39 CEST schrieb Andrew Jones: >> Hi Heiko, >> >> Please use a cover-letter for a patch series. They allow the series to be >> threaded better and people can reply to the cover-letter with series-wide >> comments. For example, I'd like to reply to a cover-letter now with >> >> For the series >> >> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> >> >> but now it looks like I need to go back and reply to each patch >> separately. > > I'm not sure if tooling like b4 can handle Reviewed-by's in cover-letters.
Yup, it can! At least `b4 {am,shazam} -t` will. I am not sure if the new `b4 trailers` does.
> At least some time back it couldn't, so am not sure if that was added > meanwhile. So tags added to cover-letters might even get lost. > > But I'll add a cover-letter nevertheless - need a place for the v2 changelog > anyway :-) > > Heiko > > >> >> Thanks, >> drew >> >> On Fri, Sep 02, 2022 at 12:27:41AM +0200, Heiko Stuebner wrote: >>> This can also do without the ifdef and use IS_ENABLED instead and >>> for better readability, getting rid of that switch also seems >>> waranted. >>> >>> Signed-off-by: Heiko Stuebner <heiko@sntech.de> >>> --- >>> arch/riscv/kernel/cpufeature.c | 13 +++++-------- >>> 1 file changed, 5 insertions(+), 8 deletions(-) >>> >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>> index 553d755483ed..764ea220161f 100644 >>> --- a/arch/riscv/kernel/cpufeature.c >>> +++ b/arch/riscv/kernel/cpufeature.c >>> @@ -253,16 +253,13 @@ void __init riscv_fill_hwcap(void) >>> #ifdef CONFIG_RISCV_ALTERNATIVE >>> static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) >>> { >>> -#ifdef CONFIG_RISCV_ISA_SVPBMT >>> - switch (stage) { >>> - case RISCV_ALTERNATIVES_EARLY_BOOT: >>> + if (!IS_ENABLED(CONFIG_RISCV_ISA_SVPBMT)) >>> return false; >>> - default: >>> - return riscv_isa_extension_available(NULL, SVPBMT); >>> - } >>> -#endif >>> >>> - return false; >>> + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) >>> + return false; >>> + >>> + return riscv_isa_extension_available(NULL, SVPBMT); >>> } >>> >>> static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) >> > > > >
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