Messages in this thread | | | From | George Pee <> | Date | Mon, 12 Sep 2022 13:09:17 -0500 | Subject | Re: [PATCH] Report support for optional ARMv8.2 half-precision floating point extension |
| |
On Mon, Sep 12, 2022 at 8:05 AM Russell King (Oracle) <linux@armlinux.org.uk> wrote: > > On Fri, Sep 09, 2022 at 04:05:53PM +0100, Catalin Marinas wrote: > > On Fri, Sep 09, 2022 at 09:57:39AM -0500, George Pee wrote: > > > The details are here. I originally thought it was a compiler bug > > > because it first showed up after a toolchain update. > > > > > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106763 > > > > > > Since FP16 is an optional extension, wouldn't it be beneficial to a > > > user who compiled some userspace float16 code using gcc > > > -mcpu=cortex-a55 which ran on a cortex-a55 with FP16 extensions but > > > SIGILL'd on a cortex-a55 w/o FP16? > > > > (please don't top-post) > > > > My point is that if the kernel doesn't have full support for FP16, it > > shouldn't advertise it to user even if the hardware supports it. If you > > fix the kernel to properly handle FP16 on supporting hardware, then the > > HWCAP part is fine by me. > > Presumably, the only CPUs that are going to support FP16 will have > non-trapping floating point, so the support code shouldn't be entered > at any time to emulate a half-precision instruction, but only to > handle the lazy restore of the thread's floating point registers? > > -- > RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ > FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
I didn't see this until after I submitted v2 of the patch. Let me take a look at the fp emulation code path. I had assumed that CP9 handling would work just like CP10/CP11 does in entry-armv.S and wouldn't need any special handling.
| |