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    SubjectRe: [PATCH v1 3/5] fpga: dfl: Add DFHv1 Register Definitions
    On 2022-09-06 at 12:04:24 -0700, matthew.gerlach@linux.intel.com wrote:
    > From: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com>
    >
    > This patch adds the definitions for DFHv1 header and related register
    > bitfields.
    >
    > Signed-off-by: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com>
    > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
    > ---
    > include/linux/dfl.h | 37 +++++++++++++++++++++++++++++++++++++
    > 1 file changed, 37 insertions(+)
    >
    > diff --git a/include/linux/dfl.h b/include/linux/dfl.h
    > index b5accdcfa368..61bcf20c1bc8 100644
    > --- a/include/linux/dfl.h
    > +++ b/include/linux/dfl.h
    > @@ -23,6 +23,16 @@
    > #define GUID_H 0x10
    > #define NEXT_AFU 0x18
    >
    > +/*
    > + * DFHv1 Register Offset definitons
    > + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA
    > + * as common header registers
    > + */
    > +#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */
    > +#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */
    > +#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */
    > +#define DFHv1_PARAM_DATA 0x8 /* Offset of Param data from Param header */
    > +
    > #define DFH_SIZE 0x8
    >
    > /* Device Feature Header Register Bitfield */
    > @@ -30,8 +40,35 @@
    > #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
    > #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
    > #define DFH_EOL BIT_ULL(40) /* End of list */
    > +#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */
    > #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
    >
    > +/*
    > + * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start),

    Reduce one whitespace indent.

    > + * 1'b1 = absolute (ARM or other non-PCIe use)
    > + */
    > +#define DFHv1_CSR_ADDR_REL BIT_ULL(0)
    > +
    > +/*
    > + * CSR Header Register Bit Definitions
    > + */

    Use oneline style comment should be OK?

    > +#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */
    > +
    > +/*
    > + * CSR SIZE Goup Register Bit Definitions
    > + */

    Same concern

    > +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */
    > +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
    > +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */
    > +#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
    > +
    > +/*
    > + * PARAM Header Register Bit Definitions
    > + */

    Same

    > +#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */
    > +#define DFHv1_PARAM_HDR_VERSION GENMASK_ULL(31, 16) /* Version Param */
    > +#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 32) /* Offset of next Param */
    > +
    > /**
    > * enum dfl_id_type - define the DFL FIU types
    > */
    > --
    > 2.25.1
    >

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