lkml.org 
[lkml]   [2022]   [Sep]   [1]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v3 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
    Date
    In today's edition of moving things around:

    The PCIe root port on PolarFire SoC is more part of the FPGA than of
    the Core Complex. It is located on the other side of the chip and,
    apart from its interrupts, most of its configuration is determined
    by the FPGA bitstream rather. This includes:

    - address translation in both directions
    - the addresses at which the config and data regions appear to the
    core complex
    - the clocks used by the AXI bus
    - the plic interrupt used

    Moving the PCIe node to the -fabric.dtsi makes it clearer than a
    singular configuration for root port is not correct & allows the
    base SoC dtsi to be more easily included.

    Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
    ---
    .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 32 +++++++++++++++++--
    .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++++++++++++++++
    arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 -----------------
    3 files changed, 58 insertions(+), 32 deletions(-)

    diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
    index c0fb9dd7b2c8..a21440c8ee03 100644
    --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
    +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
    @@ -37,8 +37,34 @@ fabric_clk1: fabric-clk1 {
    #clock-cells = <0>;
    clock-frequency = <125000000>;
    };
    -};

    -&pcie {
    - dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
    + pcie: pcie@2000000000 {
    + compatible = "microchip,pcie-host-1.0";
    + #address-cells = <0x3>;
    + #interrupt-cells = <0x1>;
    + #size-cells = <0x2>;
    + device_type = "pci";
    + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
    + reg-names = "cfg", "apb";
    + bus-range = <0x0 0x7f>;
    + interrupt-parent = <&plic>;
    + interrupts = <119>;
    + interrupt-map = <0 0 0 1 &pcie_intc 0>,
    + <0 0 0 2 &pcie_intc 1>,
    + <0 0 0 3 &pcie_intc 2>,
    + <0 0 0 4 &pcie_intc 3>;
    + interrupt-map-mask = <0 0 0 7>;
    + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
    + clock-names = "fic0", "fic1", "fic3";
    + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
    + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
    + msi-parent = <&pcie>;
    + msi-controller;
    + status = "disabled";
    + pcie_intc: interrupt-controller {
    + #address-cells = <0>;
    + #interrupt-cells = <1>;
    + interrupt-controller;
    + };
    + };
    };
    diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
    index 49380c428ec9..67303bc0e451 100644
    --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
    +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
    @@ -13,4 +13,33 @@ fabric_clk1: fabric-clk1 {
    #clock-cells = <0>;
    clock-frequency = <125000000>;
    };
    +
    + pcie: pcie@2000000000 {
    + compatible = "microchip,pcie-host-1.0";
    + #address-cells = <0x3>;
    + #interrupt-cells = <0x1>;
    + #size-cells = <0x2>;
    + device_type = "pci";
    + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
    + reg-names = "cfg", "apb";
    + bus-range = <0x0 0x7f>;
    + interrupt-parent = <&plic>;
    + interrupts = <119>;
    + interrupt-map = <0 0 0 1 &pcie_intc 0>,
    + <0 0 0 2 &pcie_intc 1>,
    + <0 0 0 3 &pcie_intc 2>,
    + <0 0 0 4 &pcie_intc 3>;
    + interrupt-map-mask = <0 0 0 7>;
    + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
    + clock-names = "fic0", "fic1", "fic3";
    + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
    + msi-parent = <&pcie>;
    + msi-controller;
    + status = "disabled";
    + pcie_intc: interrupt-controller {
    + #address-cells = <0>;
    + #interrupt-cells = <1>;
    + interrupt-controller;
    + };
    + };
    };
    diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
    index 74493344ea41..b1b7964608e3 100644
    --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
    +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
    @@ -464,35 +464,6 @@ usb: usb@20201000 {
    status = "disabled";
    };

    - pcie: pcie@2000000000 {
    - compatible = "microchip,pcie-host-1.0";
    - #address-cells = <0x3>;
    - #interrupt-cells = <0x1>;
    - #size-cells = <0x2>;
    - device_type = "pci";
    - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
    - reg-names = "cfg", "apb";
    - bus-range = <0x0 0x7f>;
    - interrupt-parent = <&plic>;
    - interrupts = <119>;
    - interrupt-map = <0 0 0 1 &pcie_intc 0>,
    - <0 0 0 2 &pcie_intc 1>,
    - <0 0 0 3 &pcie_intc 2>,
    - <0 0 0 4 &pcie_intc 3>;
    - interrupt-map-mask = <0 0 0 7>;
    - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
    - clock-names = "fic0", "fic1", "fic3";
    - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
    - msi-parent = <&pcie>;
    - msi-controller;
    - status = "disabled";
    - pcie_intc: interrupt-controller {
    - #address-cells = <0>;
    - #interrupt-cells = <1>;
    - interrupt-controller;
    - };
    - };
    -
    mbox: mailbox@37020000 {
    compatible = "microchip,mpfs-mailbox";
    reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
    --
    2.36.1
    \
     
     \ /
      Last update: 2022-09-01 15:39    [W:5.498 / U:0.100 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site