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    SubjectRe: [PATCH 2/2] net: ethernet: stmicro: stmmac: dwmac-rk: Add rv1126 support
    On Thu, Sep 01, 2022 at 12:56:09PM +0530, Jagan Teki wrote:
    > On Mon, 29 Aug 2022 at 18:40, Andrew Lunn <andrew@lunn.ch> wrote:
    > >
    > > On Mon, Aug 29, 2022 at 06:50:42AM +0000, Anand Moon wrote:
    > > > Rockchip RV1126 has GMAC 10/100/1000M ethernet controller
    > > > via RGMII and RMII interfaces are configured via M0 and M1 pinmux.
    > > >
    > > > This patch adds rv1126 support by adding delay lines of M0 and M1
    > > > simultaneously.
    > >
    > > What does 'delay lines' mean with respect to RGMII?
    >
    > These are MAC receive clock delay lengths.
    >
    > >
    > > The RGMII signals need a 2ns delay between the clock and the data
    > > lines. There are three places this can happen:
    > >
    > > 1) In the PHY
    > > 2) Extra long lines on the PCB
    > > 3) In the MAC
    > >
    > > Generally, 1) is used, and controlled via phy-mode. A value of
    > > PHY_INTERFACE_MODE_RGMII_ID passed to the PHY driver means it will add
    > > these delays.
    > >
    > > You don't want both the MAC and the PHY adding delays.
    >
    > Yes, but these are specific to MAC, not related to PHY delays. Similar
    > to what is there in other Rockchip SoC families like RK3366, 3368,
    > 3399, 3128, but these MAC clock delay lengths are grouped based on the
    > iomux group in RV1126. We have iomux group 0 (M0) and group 1 (M1), so
    > the rgmii has to set these lengths irrespective of whether PHY add's
    > or not.

    So this is just fine tuning, in the order of pico seconds?

    If that is all it is, then this is fine. It becomes a problem when it
    is 2ns.

    Andrew

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