Messages in this thread | | | Date | Thu, 1 Sep 2022 08:30:49 +0200 | From | Robert Richter <> | Subject | Re: [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities |
| |
On 31.08.22 11:52:24, Jonathan Cameron wrote: > On Wed, 31 Aug 2022 10:15:56 +0200 > Robert Richter <rrichter@amd.com> wrote:
> > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > > index ffdf439adb87..f9cdf23a91a8 100644 > > --- a/drivers/cxl/acpi.c > > +++ b/drivers/cxl/acpi.c > > @@ -322,6 +322,8 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host) > > { > > struct pci_bus *bus = host ? host->bus : NULL; > > struct acpi_device *adev; > > + struct pci_dev *pdev; > > + bool is_restricted_host; > > > > while ((bus = pci_find_next_bus(bus)) != NULL) { > > host = bus ? to_pci_host_bridge(bus->bridge) : NULL; > > @@ -343,6 +345,20 @@ struct pci_host_bridge *cxl_find_next_rch(struct pci_host_bridge *host) > > dev_dbg(&host->dev, "PCI ACPI host found: %s\n", > > acpi_dev_name(adev)); > > > > + /* Check CXL DVSEC of dev 0 func 0 */ > > So assumption here is that the hostbridge has a one or more RCiEPs. > The spec (r3.0 9.11.4) allows for the EP to appear behind a root port > - that case always felt odd to me, so I'm fine with not supporting it until > we see a user.
The software view of an RCD is always the same, it shows up always as an RCiEP. See figure 9-12 and 9-13 of the spec.
-Robert
> > > + pdev = pci_get_slot(bus, PCI_DEVFN(0, 0)); > > + is_restricted_host = pdev > > + && (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) > > + && pci_find_dvsec_capability(pdev, > > + PCI_DVSEC_VENDOR_ID_CXL, > > + CXL_DVSEC_PCIE_DEVICE); > > + pci_dev_put(pdev); > > + > > + if (!is_restricted_host) > > + continue; > > + > > + dev_dbg(&host->dev, "CXL restricted host found\n"); > > + > > return host; > > }
| |