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Subject[PATCH v1 2/2] PCI: dwc: add support for 64-bit MSI target address
From
Since not all devices require a 32-bit MSI address, add support to the
PCIe host driver to allow setting the DMA mask to 64-bits. This allows
kernels to disable ZONE_DMA32 and bounce buffering (swiotlb) without
risking not being able to get a 32-bit address during DMA allocation.
Basically, in the slim chance that there are no 32-bit allocations
available, the current PCIe host driver will fail to allocate the
msi_msg page due to a DMA address overflow (seen in [1]). With this
patch, the PCIe driver can advertise 64-bit support via it's MSI
capabilities to hint to the PCIe host driver to set the DMA mask to
64-bits.

[1] https://lore.kernel.org/all/Yo0soniFborDl7+C@google.com/

Signed-off-by: Will McVicker <willmcvicker@google.com>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++++++--
drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++++
drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 0cfc3c098f13..630615719236 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -338,6 +338,8 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
struct platform_device *pdev = to_platform_device(dev);
int ret;
u32 ctrl, num_ctrls;
+ bool msi_64b = false;
+ u16 msi_capabilities;

for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
pp->irq_mask[ctrl] = ~0;
@@ -375,9 +377,17 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
dw_chained_msi_isr, pp);
}

- ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
+ msi_capabilities = dw_pcie_msi_capabilities(pci);
+ if (msi_capabilities & PCI_MSI_FLAGS_ENABLE)
+ msi_64b = msi_capabilities & PCI_MSI_FLAGS_64BIT ? true : false;
+
+ dev_dbg(dev, "Setting MSI DMA mask to %s-bit.\n",
+ msi_64b ? "64" : "32");
+ ret = dma_set_mask_and_coherent(dev, msi_64b ?
+ DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
if (ret)
- dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
+ dev_warn(dev, "Failed to set DMA mask to %s-bit.\n",
+ msi_64b ? "64" : "32");

pp->msi_page = dma_alloc_coherent(dev, PAGE_SIZE, &pp->msi_data,
GFP_KERNEL);
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index c6725c519a47..8ed402307d7f 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -82,6 +82,15 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
}
EXPORT_SYMBOL_GPL(dw_pcie_find_capability);

+u16 dw_pcie_msi_capabilities(struct dw_pcie *pci)
+{
+ u8 offset;
+
+ offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
+ return dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_msi_capabilities);
+
static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
u8 cap)
{
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 09b887093a84..70a251c8f72b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -432,6 +432,7 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp);
int dw_pcie_allocate_domains(struct dw_pcie_rp *pp);
void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
int where);
+u16 dw_pcie_msi_capabilities(struct dw_pcie *pci);
#else
static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)
{
@@ -462,6 +463,11 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,
{
return NULL;
}
+
+static inline u16 dw_pcie_msi_capabilities(struct dw_pcie *pci)
+{
+ return 0;
+}
#endif

#ifdef CONFIG_PCIE_DW_EP
--
2.37.1.559.g78731f0fdb-goog
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