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    Subject[PATCH AUTOSEL 5.19 41/58] ARM: dts: qcom: sdx55: Fix the IRQ trigger type for UART
    Date
    From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

    [ Upstream commit ae500b351ab0006d933d804a2b7507fe1e98cecc ]

    The trigger type should be LEVEL_HIGH. So fix it!

    Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
    Link: https://lore.kernel.org/r/20220530080842.37024-2-manivannan.sadhasivam@linaro.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
    index 1c2b208a5670..ef1da28f567c 100644
    --- a/arch/arm/boot/dts/qcom-sdx55.dtsi
    +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
    @@ -206,7 +206,7 @@ gcc: clock-controller@100000 {
    blsp1_uart3: serial@831000 {
    compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
    reg = <0x00831000 0x200>;
    - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
    + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&gcc 30>,
    <&gcc 9>;
    clock-names = "core", "iface";
    --
    2.35.1
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