Messages in this thread | | | Date | Sat, 6 Aug 2022 11:01:06 +0200 | From | Ingo Molnar <> | Subject | Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry |
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* Dave Hansen <dave.hansen@intel.com> wrote:
> On 8/5/22 10:30, ira.weiny@intel.com wrote: > > +static inline void arch_save_aux_pt_regs(struct pt_regs *regs) > > +{ > > + struct pt_regs_auxiliary *aux_pt_regs = &to_extended_pt_regs(regs)->aux; > > + > > + aux_pt_regs->cpu = raw_smp_processor_id(); > > +} > > This is in a fast path that all interrupt and exception entry uses. So, > I was curious what the overhead is. > > Code generation in irqentry_enter() gets a _bit_ more complicated > because arch_save_aux_pt_regs() has to be done on the way out of the > function and the compiler can't (for instance) do a > > mov $0x1,%eax > ret > > to return. But, the gist of the change is still only two instructions > that read a pretty hot, read-only per-cpu cacheline: > > mov %gs:0x7e21fa4a(%rip),%eax # 15a38 <cpu_number> > mov %eax,-0x8(%rbx) > > That doesn't seem too bad.
It's still 2 instructions more than what we had before, while the fault-time CPU number is only needed infrequently AFAICS.
Thanks,
Ingo
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