Messages in this thread Patch in this message | | | From | Matt Ranostay <> | Subject | [PATCH] arm64: dts: ti: k3-j7200: fix main pinmux range | Date | Fri, 5 Aug 2022 10:43:39 -0700 |
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Range size of 0x2b4 was incorrect since there isn't 173 configurable pins for muxing. Additionally there is a non-addessable region in the mapping which requires spliting into two ranges.
main_pmx0 -> 71 pins main_pmx1 -> 2 pins
Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Matt Ranostay <mranostay@ti.com> --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 16684a2f054d..a713de57056f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -295,7 +295,16 @@ cpts@310d0000 { main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x11c000 0x00 0x2b4>; + reg = <0x00 0x11c000 0x00 0x10c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_pmx1: pinctrl@11c164 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x11c164 0x00 0x8>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; -- 2.36.1
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