Messages in this thread | | | From | Andrei Vagin <> | Date | Fri, 5 Aug 2022 05:12:23 -0700 | Subject | Re: [patch V4 09/65] x86/fpu: Sanitize xstateregs_set() |
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On Thu, Jul 28, 2022 at 4:32 PM Chang S. Bae <chang.seok.bae@intel.com> wrote: > > On 7/25/2022 2:26 PM, Dave Hansen wrote: > > > > Do you happen to have a quick reproducer for this, or at least the > > contents of the buffer that you are trying to restore? > > While not following this report, I think there is a regression along > with the changes: > > As looking into the spec, this state load does not depend on XSTATE_BV: > > RFBM := XCR0 AND EDX:EAX; > COMPMASK := XCOMP_BV field from XSAVE header; > > IF COMPMASK[63] = 0 > THEN > ... > IF RFBM[1] = 1 OR RFBM[2] = 1 > THEN load MXCSR from legacy region of XSAVE area; > FI; > ... > ELSE > ... > > But our upstream code does reference XSTATE_BV instead of RFBM [1,2]. > > My test case [3] fails with the upstream but works with 5.13, which is > before the series. Then, this change looks to make it work at least for it:
gVisor test passes with this change too. Chang, are you going to send a patch?
Thanks, Andrei
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