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SubjectRe: [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry
On Fri, Aug 05, 2022 at 12:07:57PM +0000, Conor.Dooley@microchip.com wrote:
> On 05/08/2022 12:05, Mark Brown wrote:

> >> +++ b/MAINTAINERS
> >> @@ -17146,6 +17146,7 @@ S: Supported
> >> F: arch/riscv/boot/dts/microchip/
> >> F: drivers/mailbox/mailbox-mpfs.c
> >> F: drivers/soc/microchip/
> >> +F: drivers/spi/spi-microchip-core-qspi.c
> >> F: drivers/spi/spi-microchip-core.c
> >> F: include/soc/microchip/mpfs.h

> > You should also add a pattern for the DT binding here.

> All of the bindings for the platform should have entries then
> right? I'll send a separate patch adding all of the missing
> bindings. I have a deferred change to the entry that needs to
> be sent to Arnd anyway so I can queue the two together.
> Nothing to be gained by waiting until this driver lands in 6.1+
> to have MAINTAINERS coverage of the bindings :)

Yes, it's better if everything has coverage - that way the platform
maintainers are more likely to see any changes that are needed for the
bindings. Sending as part of a bigger patch adding the rest sounds
good.
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