Messages in this thread | | | Date | Thu, 4 Aug 2022 12:26:48 +0200 | Subject | Re: [PATCH] dt-bindings: riscv: fix SiFive l2-cache's cache-sets | From | Krzysztof Kozlowski <> |
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On 03/08/2022 20:54, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Fix device tree schema validation error messages for the SiFive > Unmatched: ' cache-sets:0:0: 1024 was expected'. > > The existing bindings allow for just 1024 cache-sets but the fu740 on > Unmatched the has 2048 cache-sets. The ISA itself permits any arbitrary > power of two, however this is not supported by dt-schema. The RTL for > the IP, to which the number of cache-sets is a tunable parameter, has > been released publicly so speculatively adding a small number of > "reasonable" values seems unwise also. > > Instead, as the binding only supports two distinct controllers: add 2048 > and explicitly lock it to the fu740's l2 cache while limiting 1024 to > the l2 cache on the fu540. > > Fixes: af951c3a113b ("dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740") > Reported-by: Atul Khare <atulkhare@rivosinc.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > I split this off from the existing series as there is no dependancy > between this cache change and the gpio patch. The prior series can > be found at: > https://lore.kernel.org/all/20220726170725.3245278-2-mail@conchuod.ie/ > ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards, Krzysztof
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