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Subject[RESEND PATCH] dt-bindings: sifive-ccache: fix cache level for l3 cache
Date
With newer cores such as the p550, the SiFive composable cache can be
a level 3 cache. Update the cache level to be one of 2 or 3.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
Documentation/devicetree/bindings/riscv/sifive-ccache.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
index 1a64a5384e36..6190deb65455 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
@@ -45,7 +45,7 @@ properties:
const: 64

cache-level:
- const: 2
+ enum: [2, 3]

cache-sets:
enum: [1024, 2048]
--
2.35.1
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