Messages in this thread | | | Date | Tue, 30 Aug 2022 10:43:38 +0530 | From | Vinod Koul <> | Subject | Re: [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g |
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On 28-06-22, 15:22, Roger Quadros wrote: > Hi, > > The SERDES in J7200 SR2.0 supports 2 reference clocks. > The second reference clock (core_ref1_clk) is hardwired to > MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz). > > Add a new compatible "j7200-wiz-10g" for this device. > > The external clocks to SERDES PLL refclock mapping is now > controlled by a special register in System Control Module > (SCM) space. Add a property "ti,scm" to reference it and > configure it in the driver.
Applied, thanks
-- ~Vinod
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