Messages in this thread | | | From | Hongxing Zhu <> | Subject | RE: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support | Date | Wed, 31 Aug 2022 00:38:51 +0000 |
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> -----Original Message----- > From: Philipp Zabel <p.zabel@pengutronix.de> > Sent: 2022年8月31日 0:46 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de; > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org; > shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com; > marex@denx.de; richard.leitner@linux.dev > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com> > Subject: Re: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST > support > > Hi, > > On Di, 2022-08-30 at 15:46 +0800, Richard Zhu wrote: > > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST > > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1. > > But i.MX8MP has one inversed default value 1b'0 of PERST bit. > > > > And the PERST bit should be kept 1b'1 after power and clocks are stable. > > So fix the i.MX8MP PCIe PHY PERST support here. > > > > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC") > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> > > Tested-by: Marek Vasut <marex@denx.de> > > Tested-by: Richard Leitner <richard.leitner@skidata.com> > > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> > > I've applied this patch to the reset/fixes branch. >
Thanks a lot.
Best Regards Richard Zhu
> regards > Philipp
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